A new soft-error-immune DRAM cell using a stacked CMOS structure

A new VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFET´s and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both storage capacitor nodes are kept electrically floating in retention periods and one storage capacitor node is formed in a thin SOI film, an alpha-particle hit does not destroy the stored charge of this memory cell. It is sufficient for an SOI-PMOSFET to provide only three orders of magnitude ON/OFF current ratio. Experimental memory cells were fabricated using polysilicon film as an SOI film. Measuring them confirmed the main effectiveness of this memory cell.