DocumentCode
1117073
Title
Orientation and ion-implanted transverse effects in self-aligned GaAs MESFET´s
Author
Chen, Chung-Hsu ; Peczalski, Andrzej ; Shur, Michael S. ; Chung, Ho-Kyoon
Author_Institution
Honeywell, Inc., Bloomington, MN
Volume
34
Issue
7
fYear
1987
fDate
7/1/1987 12:00:00 AM
Firstpage
1470
Lastpage
1481
Abstract
The orientation dependence of the threshold voltage and device transconductance of ion-implanted GaAs FET\´s has been investigated and modeled. The threshold voltages of the devices along the [011] and [01
] directions are different when the gate length is short (≤ 3 µm). Experimental results and theoretical calculations show that this is primarily due to the strain in the active channel, induced by the dielectric overlayer. For the short self-aligned gate structure, the lateral spread of the ion-implanted n+layer is important as well. When these two effects are taken into account, calculated results agree well with the experimental data for standard self-aligned gate structures, and self-aligned structures with a sidewall or T-gate, fabricated using lamp- or furnace-annealing processes. This model also allows us to simulate the threshold voltage and transconductance dependence on the annealing time for different device parameters (such as gate length and channel doping)and process variables (i.e., sidewall or T-gate dimensions and impurity diffusion constant). We also calculated the gate length dependence of the transconductance for devices fabricated using a sidewall process. Results of this calculation are compared with the experimental data for different sidewall thicknesses.
] directions are different when the gate length is short (≤ 3 µm). Experimental results and theoretical calculations show that this is primarily due to the strain in the active channel, induced by the dielectric overlayer. For the short self-aligned gate structure, the lateral spread of the ion-implanted n+layer is important as well. When these two effects are taken into account, calculated results agree well with the experimental data for standard self-aligned gate structures, and self-aligned structures with a sidewall or T-gate, fabricated using lamp- or furnace-annealing processes. This model also allows us to simulate the threshold voltage and transconductance dependence on the annealing time for different device parameters (such as gate length and channel doping)and process variables (i.e., sidewall or T-gate dimensions and impurity diffusion constant). We also calculated the gate length dependence of the transconductance for devices fabricated using a sidewall process. Results of this calculation are compared with the experimental data for different sidewall thicknesses.Keywords
Capacitive sensors; Dielectrics; FETs; Gallium arsenide; Impurities; MESFETs; Semiconductor process modeling; Simulated annealing; Threshold voltage; Transconductance;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1987.23108
Filename
1486819
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