• DocumentCode
    1118121
  • Title

    Latchup performance of retrograde and conventional n-well CMOS technologies

  • Author

    Lewis, Alan G. ; Martin, Russel A. ; Huang, Tiao-Yuan ; Chen, John Y. ; Koyanagi, Mitsumasa

  • Author_Institution
    Xerox Palo Alto Research Center, Palo Alto, CA
  • Volume
    34
  • Issue
    10
  • fYear
    1987
  • fDate
    10/1/1987 12:00:00 AM
  • Firstpage
    2156
  • Lastpage
    2164
  • Abstract
    The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+epitaxial material.
  • Keywords
    CMOS technology; Circuits; Doping; Epitaxial layers; Ion implantation; Isolation technology; Oxidation; Semiconductor device modeling; Silicon; Substrates;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1987.23211
  • Filename
    1486922
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1118121