• DocumentCode
    1118805
  • Title

    Optimizing Sequential Cycles Through Shannon Decomposition and Retiming

  • Author

    Soviani, Cristian ; Tardieu, Olivier ; Edwards, Stephen A.

  • Author_Institution
    Dept. of Comput. Sci., Columbia Univ., New York, NY
  • Volume
    26
  • Issue
    3
  • fYear
    2007
  • fDate
    3/1/2007 12:00:00 AM
  • Firstpage
    456
  • Lastpage
    467
  • Abstract
    Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pipelines, but it is stymied by tight sequential cycles. Designers usually attack such cycles by manually combining Shannon decomposition with retiming-effectively a form of speculation-but such manual decomposition is error prone. We propose an efficient algorithm that simultaneously applies Shannon decomposition and retiming to optimize circuits with tight sequential cycles. While the algorithm is only able to improve certain circuits (roughly half of the benchmarks we tried), the performance increase can be dramatic (7%-61%) with only a modest increase in area (1%-12%). The algorithm is also fast, making it a practical addition to a synthesis flow
  • Keywords
    circuit optimisation; pipeline processing; sequential circuits; timing circuits; Shannon decomposition; circuit synthesis; circuits optimization; packet processing; pipelines processing; retiming; sequential cycles; sequential logic circuits; Circuit synthesis; Clocks; Delay; Digital circuits; Feedback loop; Logic circuits; Multiplexing; Pipelines; Registers; Sequential circuits; Circuit optimization; circuit synthesis; encoding; sequential logic circuits;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.890583
  • Filename
    4100763