DocumentCode :
1118841
Title :
Timing-Aware Power-Noise Reduction in Placement
Author :
Yeh, Chao-Yang ; Merek-Sadowska, Malgorzata
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA
Volume :
26
Issue :
3
fYear :
2007
fDate :
3/1/2007 12:00:00 AM
Firstpage :
527
Lastpage :
541
Abstract :
We describe a placement-level decoupling capacitance (decap) insertion technique whose objective is to reduce power noise, taking into account circuit timing. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells that, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors that switch infrequently, it is unlikely that this cell will suffer from a power-noise problem. Based on the cell power-noise estimation, we add decap padding to each cell. Then, we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can allocate decaps to improve power noise, power consumption, and timing. We propose two gate-sizing algorithms. The first one uses a sequence of linear programs (SLP) formulation, and the second one uses a budgeting-based heuristic algorithm. The SLP algorithm can produce better power-noise results than the heuristic, at the expense of runtime. Experimental results show that our techniques can effectively reduce power noise and still meet timing constraints
Keywords :
integrated circuit noise; interference suppression; power grids; power integrated circuits; timing circuits; IR drop; circuit timing; decoupling capacitance insertion; gate sizing; heuristic algorithm; noise estimation; power grid noise; power noise reduction; power timing; sequence of linear programs; standard cell placement tool; switching frequency; timing aware; Capacitance; Circuit noise; Energy consumption; Frequency estimation; Noise reduction; Performance analysis; Power grids; Switches; Switching frequency; Timing; IR drop (IRD); placement; power noise;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2006.883917
Filename :
4100766
Link To Document :
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