Computational Cost of Image Registration with a Parallel Binary Array Processor

Author

Reeves, A.P. ; Rostampour, A.

Author_Institution

School of Electrical Engineering, Purdue University, West Lafayette, IN 47907.

Issue

4

fYear

1982

fDate

7/1/1982 12:00:00 AM

Firstpage

449

Lastpage

455

Abstract

The application of a simulated binary array processor (BAP) to the rapid analysis of a sequence of images has been studied. Several algorithms have been developed which may be implemented on many existing parallel processing machines. The characteristic operations of a BAP are discussed and analyzed. A set of preprocessing algorithms are described which are designed to register two images of TV-type video data in real time. These algorithms illustrate the potential uses of a BAP and their cost is analyzed in detail. The results of applying these algorithms to FLIR data and to noisy optical data are given. An analysis of these algorithms illustrates the importance of an efficient global feature extraction hardware for image understanding applications.

Keywords

Algorithm design and analysis; Analytical models; Computational efficiency; Computational modeling; Costs; Image analysis; Image registration; Image sequence analysis; Parallel processing; Registers; Binary array processor (BAP); bit-serial algorithms; computation cost; image registration; parallel processing; real-time processing; sequential image analysis;

fLanguage

English

Journal_Title

Pattern Analysis and Machine Intelligence, IEEE Transactions on

Publisher

ieee

ISSN

0162-8828

Type

jour

DOI

10.1109/TPAMI.1982.4767280

Filename

4767280