Design Verification at the Register Transfer Language Level

Computer description languages can be used as input to software tools which aid in the design of digital hardware structures. One of the important phases in the design process is verification. A software system is described which aids the verification process of a computer description at the register transfer language (RTL) leveL. It is based on the concept of concurrent simulation and comparison of the functional and the structural description of a computer. Error types, in particular consistency and semantic errors, and algorithms for their detection are discussed. The tools necessary to implement these detection procedures are outlined.