DocumentCode
1119125
Title
Analysis of Memory Interference in Multiprocessors
Author
Bhandarkar, Dileep P.
Author_Institution
Texas Instruments,Incorporated
Issue
9
fYear
1975
Firstpage
897
Lastpage
908
Abstract
This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.
Keywords
Analytic models, Markov chains, memory interference, multiprocessors, performance measurement, simulation.; Analytical models; Computational modeling; Interference; Mathematical analysis; Mathematical model; Measurement; Multiprocessing systems; Predictive models; Switches; Time sharing computer systems; Analytic models, Markov chains, memory interference, multiprocessors, performance measurement, simulation.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1975.224335
Filename
1672928
Link To Document