Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM´s

Author

Sakata, Takeshi ; Itoh, Kiyoo ; Horiguchi, Masashi ; Aoki, Masakazu

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

29

Issue

8

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

887

Lastpage

894

Abstract

A two-dimensional power-line selection scheme for an iterative CMOS circuit block is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks in a two-dimensional arrangement and selectively energized by two-dimensional power-line selection. It is shown to be suitable for dual word-line structure, particularly because of its single sub-word line activation. This scheme achieves a very large reduction of active current to one sixteenth, from 116 mA to 22 mA for a 1-V 16-Gb DRAM with dual word-line structure, while maintaining a speed comparable to existing multi-megabit DRAM´s. The proposed scheme is promising for reducing the active power of future multi-gigabit DRAM´s

Keywords

CMOS integrated circuits; DRAM chips; VLSI; 1 V; 16 Gbit; 22 mA; 2D power-line selection scheme; CMOS dynamic RAM; dual word-line structure; iterative CMOS circuit block; low subthreshold-current; multi-gigabit DRAM; single sub-word line activation; two-dimensional power-line selection; CMOS logic circuits; Capacitance; DRAM chips; Frequency; MOSFETs; Random access memory; Stress; Subthreshold current; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.297692

Filename

297692