A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering

Author

Henriques, Bernardo G. ; Franca, José E.

Author_Institution

Dept. of Electr. & Comput. Eng., Inst. Superior Tecnico, Lisbon, Portugal

Volume

29

Issue

8

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

972

Lastpage

977

Abstract

This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply

Keywords

CMOS integrated circuits; delay lines; digital filters; digital-analogue conversion; 1.2 micron; 115 mW; 13.3 mA; 18 MHz; 5 V; 54 MHz; D/A conversion; FIR filtering; digital CMOS technology; digital delay lines; full-scale output current; high-speed programmable CMOS interface system; integrated circuit design; programmable delay length; steering-current D/A converters; CMOS digital integrated circuits; CMOS integrated circuits; CMOS technology; Clocks; Delay lines; Digital filters; Filtering; Finite impulse response filter; High speed integrated circuits; Prototypes;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.297706

Filename

297706