Title :
A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization
Author :
Burghartz, Joachim N. ; McIntosh, Robert C. ; Stanis, Carol L.
Author_Institution :
Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
8/1/1994 12:00:00 AM
Abstract :
A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to ≃30%, the collector-base capacitance to ≃70%, and the extrinsic base contact resistance to <50% compared to trench isolation. The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology
Keywords :
BiCMOS integrated circuits; capacitance; circuit layout; epitaxial growth; integrated circuit technology; polishing; semiconductor-insulator boundaries; silicon; SEG steps; SOI regions; SOI-BiCMOS technology; Si; bipolar/BiCMOS isolation technology; characterization; collector-base capacitance; collector-substrate capacitance; device isolation structure; extrinsic base contact resistance; fabrication process; low-capacitance isolation technology; low-parasitic bipolar transistor integration; optimum device layout; polishing cycles; selective epitaxial growth; vertical bipolar transistors; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Capacitance; Carbon capture and storage; Epitaxial growth; Fabrication; Integrated circuit interconnections; Isolation technology; Substrates;
Journal_Title :
Electron Devices, IEEE Transactions on
