• DocumentCode
    1119860
  • Title

    Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach

  • Author

    Dadda, Luigi

  • Author_Institution
    Politecnico di Milano, Milano
  • Volume
    56
  • Issue
    10
  • fYear
    2007
  • Firstpage
    1320
  • Lastpage
    1328
  • Abstract
    Decimal arithmetic has been revived in recent years due to the large amount of data in commercial applications. We consider the problem of multioperand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. We adopt the latter approach, which is particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool.
  • Keywords
    adders; binary codes; digital arithmetic; binary arithmetic; binary-coded decimal; binary-to-decimal conversion; decimal arithmetic; elementary conversion cells; multioperand parallel decimal adder; Adders; Computational modeling; Digital arithmetic; Embedded system; Hardware; Internet; Law; Legal factors; Market research; Parallel processing; Computer arithmetic; decimal arithmetic; hardware design; multioperand adders;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2007.1067
  • Filename
    4302705