An ethernet switch architecture for bandwidth provision of broadband access networks

Ethernet is one of the potential candidates capable of meeting the bandwidth demands of subscribers and successfully supporting various services in broadband access networks. However, the lack of a traffic management capability is a major obstacle to successful deployment. In this article we suggest an Ethernet switch architecture that offers performance-guaranteed broadband access services. We also discuss the micro-architecture of the switch and associated design issues. Switches in the proposed architecture identify subscriber traffic without handling higher layer protocols, regulate it with per subscriber traffic policing, and ensure deterministic network performance. The implemented switch ASIC offers 28 gigabit Ethernet ports, integrating 9 million logic gates and 51 memories holding a total of 3.4 Mb to store data and control states on a single 10 mm x 10 mm die using 0.13 mum CMOS technology. The performance evaluation results, verified using a network performance analyzer, show that the proposed architecture guarantees transfer rates of individual subscribers based on their service agreements, effectively protecting network resources from excess traffic, which adversely affects the QoS of existing users´ traffic.