CMOS Multistage Preamplifier Design for High-Speed and High-Resolution Comparators

This brief describes a design technique for multistage preamplifiers of the type commonly used in high-performance comparators. Following the examination of multistage preamplifier responses in both the spectral and time domains, and a consideration 1/f noise attenuation in topologies employing offset storage capacitors, a procedure for optimizing both the number of stages and the offset storage capacitance is presented. As a demonstration vehicle, a comparator with a 13-Msample/s conversion rate and 200-muV minimum input resolution is designed for realization in a 0.4-mum CMOS technology under the constraint of a power dissipation of 250 muW when operating from a 2.5-V supply. In this design, the effective input signal is 33 muV for the minimum input resolution of 200 muV due to signal corruption from circuit noise and residual error from incomplete settling