A Josephson systolic array processor for multiplication/addition operations

Author

Morisue, M. ; Li, Fu-Qiang ; Tobita, M. ; Kaneko, S.

Author_Institution

Dept. of Electron. Eng., Saitama Univ., Urawa, Japan

Volume

27

Issue

2

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

2855

Lastpage

2858

Abstract

A novel Josephson systolic array processor to perform multiplication/addition operations is proposed. The proposed systolic array processor consists of a set of three kinds of interconnected cells in which the main circuits are made by using SQUID gates. A multiplication of 2 b×2 b is performed in the single cell at a time, and an addition of three data with two bits is simultaneously performed in an another type of cell. Furthermore, information in this system flows between cells in a pipeline fashion so that a high performance can be achieved. The principle of Josephson systolic array processor is described in detail, and the simulation results are illustrated for the multiplication/addition of (4 b×4 b+8 b). The results show that these operations can be executed in 330 ps

Keywords

SQUIDs; digital arithmetic; pipeline processing; superconducting logic circuits; superconducting processor circuits; systolic arrays; 330 ps; Josephson systolic array processor; SQUID gates; addition; multiplication; multiplication/addition operations; pipeline; simulation results; Application software; Circuit simulation; Computational modeling; Computer applications; Equations; Integrated circuit technology; Pipelines; Prototypes; Systolic arrays; Throughput;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/20.133804

Filename

133804