Title :
Josephson 32-bit shift register
Author :
Yuh, Perng-Fei ; Yao, Chung-Ting ; Bradley, Paul
Author_Institution :
Hypres Inc., Elmsford, NY, USA
fDate :
3/1/1991 12:00:00 AM
Abstract :
A 32-b shift register designed by edge-triggered gates was tested with ±25% bias margin and ±81% input margin for the full array. Simulations showed ±55% bias margin at 3.3 GHz and worked up to a maximum frequency of 30 GHz with a junction current density of 2000 A/cm2, although the shift register has only been tested up to 500 MHz, limited by instrumentation. This edge-triggered gate, consisting of a pair of conventional Josephson logic gates in series, has the advantages of wide margins, short reset time, and insensitivity to global parameter variations
Keywords :
Josephson effect; SQUIDs; shift registers; superconducting integrated circuits; superconducting logic circuits; 32 bit; 500 MHz to 30 GHz; Josephson logic gates; edge-triggered gates; shift register; Circuits; Clocks; Critical current; Josephson junctions; Large scale integration; Logic gates; Shift registers; Switches; Testing; Voltage;
Journal_Title :
Magnetics, IEEE Transactions on
