An Area Efficient SEU-Tolerant Latch Design

Author

Wang, H.-B. ; Bi, J.-S. ; Li, M.-L. ; Chen, L. ; Liu, R. ; Li, Y.-Q. ; He, A.-L. ; Guo, G.

Author_Institution

Coll. of IOT Eng., Univ. of Saskatchewan, Saskatoon, SK, Canada

Volume

61

Issue

6

fYear

2014

fDate

Dec. 2014

Firstpage

3660

Lastpage

3666

Abstract

This paper presents a new SEU-tolerant latch design based on Quatro and NMOS feedback transistors. By using these feedback transistors, the SEU susceptibility is decreased because of the cutoff feedback loop. Simulation results demonstrate that the proposed design is immune to static single node upsets. The proposed latch and the reference Quatro were designed and fabricated on a 130 nm process. The test chip was exposed to heavy ions at the TAMU Cyclotron facility. The testing results show that the proposed design has a higher upset LET threshold and lower cross-section when compared to the reference latch. Its lower SEU vulnerability comes with small area penalty.

Keywords

MOSFET; cyclotrons; flip-flops; nuclear electronics; radiation hardening (electronics); tolerance analysis; LET threshold; NMOS feedback transistor; Quatro feedback transistor; SEU susceptibility; TAMU Cyclotron facility; area efficient SEU-tolerant latch design; cutoff feedback loop; static single node upsets; test chip; Circuit simulation; Latches; MOS devices; Single event upsets; Transistors; Charge sharing; quatro; radiation hardening; single event upset (SEU); soft error;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2361514

Filename

6926869