A double-epitaxial process for high-density DRAM trench-capacitor isolation

A new double-epi structure for isolating deep (>5 µm) trench capacitors with 1 µm or less spacing is described. This technique consists of a thin lightly doped upper epilayer on top of a thicker and more heavily doped bottom layer of epi. The low resistivity bottom epilayer is designed to isolate trench capacitors of any depth. The upper layer with high resistivity is used for the CMOS periphery and can be selectively doped to achieve a near-uniform concentration to isolate trench capacitors in the core. Isolation between deep trenches at 1.0-µm spacing has been demonstrated to be applicable for 4 Mbit and greater DRAM integration levels.