Title :
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains
Author :
Apperson, Ryan W. ; Yu, Zhiyi ; Meeuwsen, Michael J. ; Mohsenin, Tinoosh ; Baas, Bevan M.
Author_Institution :
Boston Sci. CRM Div., Redmond
Abstract :
A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18- mum CMOS full-custom design and a 0.18-mum CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580-MHz operation and 10.3-mW power dissipation while performing simultaneous FIFO read and write operations at 1.8 V.
Keywords :
CMOS digital integrated circuits; clocks; integrated circuit design; logic design; parallel processing; system-on-chip; CMOS full-custom design; CMOS standard cell design; FIFO read and write operations; arbitrary clock domains; data consumer; data transfers; frequency 580 MHz; globally asynchronous locally synchronous array processor; haltable clock domains; multiple clock cycles; power 10.3 mW; power dissipation; power efficient dual-clock first-input first-out architecture; scalable dual-clock FIFO; size 0.18 mum; systems-on-a-chip; voltage 1.8 V; CMOS process; Circuits; Clocks; Delay; Frequency; Power dissipation; Robustness; Synchronization; Timing; Very large scale integration; Asynchronous; VLSI; dual-clock first-input first-output (FIFO); scalable;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2007.903938
