DocumentCode
1122147
Title
Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural Computation Using Stochastic Logic
Author
Onomi, Takeshi ; Kondo, Taizo ; Nakajima, Koji
Author_Institution
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
Volume
19
Issue
3
fYear
2009
fDate
6/1/2009 12:00:00 AM
Firstpage
626
Lastpage
629
Abstract
We report a design and an experimental result of an SFQ up/down counter for neural computation using stochastic logic. Neural computation using stochastic logic must accumulate the pulses in order to generate the membrane potential of a neuron. A high-speed up/down counter is necessary to achieve high-speed operation. The proposed up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method. A 4-bit up/down counter is fabricated using niobium-trilayer standard process and successfully demonstrated. The numerical simulation shows that the up/down counter can operate up to 70 GHz with an enough bias margin in the accumulation phase.
Keywords
counting circuits; logic design; neural nets; superconducting logic circuits; SFQ up-down counter; fabrication process; neural computation; niobium-trilayer standard process; single flux-quantum; stochastic logic; word length 4 bit; Josephson logic; neural network hardware; single flux-quantum; stochastic logic;
fLanguage
English
Journal_Title
Applied Superconductivity, IEEE Transactions on
Publisher
ieee
ISSN
1051-8223
Type
jour
DOI
10.1109/TASC.2009.2018477
Filename
5153039
Link To Document