DocumentCode :
1122304
Title :
Exact calculation of synchronizing sequences based on binary decision diagrams
Author :
Pixley, Carl ; Jeong, Seh-Woong ; Hachtel, Gary D.
Author_Institution :
Microprocessor & Memory Technol. Group, Motorola Inc., Austin, TX, USA
Volume :
13
Issue :
8
fYear :
1994
fDate :
8/1/1994 12:00:00 AM
Firstpage :
1024
Lastpage :
1034
Abstract :
In order to reliably predict the behavior of a finite state machine (FSM) M or to generate acceptance tests for sequential designs, it is necessary to drive M to a predictable state or set of states. One possible way of accomplishing this is to have a special reset circuit to force all the latches to a specific state. However, if the circuit can be driven to a predictable state by applying an input sequence, the area required for reset circuitry can be saved. A synchronizing sequence for an FSM M is an input sequence which, when applied to any initial state of M, will drive M to a single specific state, called a reset state. An efficient and exact method for computing synchronizing sequences based on the efficient image and pre-image computation methods using binary decision diagrams is presented. The method is exact in the sense that it is a decision procedure: Given enough time and memory, the method can compute a synchronizing sequence if M has one; otherwise, the method says that M is not resettable. The theoretical heart of the proposed method is Universal Alignment, which is an analysis of the product of an FSM with itself. Algorithms and their related theorems are presented to perform the following: decide whether M has a synchronizing sequence (i.e., M is resettable), calculate a synchronizing sequence for M, calculate the set of all reset states, decide whether a specific state is a reset state. New results on the resettability of some benchmark circuits are reported
Keywords :
Boolean functions; circuit analysis computing; finite automata; finite state machines; logic CAD; sequential machines; synchronisation; Universal Alignment; binary decision diagrams; finite state machine; input sequence; pre-image computation method; predictable state; reset state; resettable FSM; sequential designs; synchronizing sequences; Automata; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Data structures; Latches; Sequential analysis; Tree graphs;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.298038
Filename :
298038
Link To Document :
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