High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz

Author

Singh, Ullas ; Green, Michael M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA, USA

Volume

40

Issue

8

fYear

2005

Firstpage

1658

Lastpage

1661

Abstract

The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-μm CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.

Keywords

CMOS analogue integrated circuits; frequency dividers; high-speed integrated circuits; integrated circuit design; microwave integrated circuits; millimetre wave integrated circuits; 0.13 micron; 1.8 V; 12 mW; 20 to 38 GHz; CMOS analogue integrated circuits; frequency conversion; high-frequency CML clock dividers; high-speed CMOS clock dividers; high-speed integrated circuits; integrated circuit design; Broadband communication; CMOS process; CMOS technology; Capacitance; Circuits; Clocks; Flip-flops; Frequency conversion; Latches; Output feedback; Broadband communication; CMOS analog integrated circuits; CMOS integrated circuits; frequency conversion; high-speed integrated circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.852420

Filename

1487609