Sub- $\hbox {100-}\mu\hbox {A}$ Reset Current of Nickel Oxide Resistive Memory Through Control of Filamentary Conductance by Current Limit of MOSFET

Resistive random access memory consisting of NiO resistive memories and control transistors was fabricated with 0.18-mum CMOS technology. An initial forming voltage as low as 2 V was achieved with thin NiO film, and a reset current lower than 100 muA was realized by using the current limit of a selected cell transistor in the set process (1T-1R). The current level was determined by its gate voltage, resulting in the control of electrical resistance of the filamentary conductive paths in the low resistive state. Furthermore, a large voltage increase in the reset operation, which may cause an undesirable set operation, was also suppressed by a voltage-clamp transistor connected to the 1T-1R cell in series. On the basis of these proposed switching schemes, the stable pulse operation was demonstrated successfully. In addition, both nonvolatile data retention at 150degC and operation in a wide temperature range (from -40degC to 150degC) were confirmed.