An efficient algorithm for selecting bipartite row or column folding of programmable logic arrays

Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead to a good guide to select row or column folding for reducing the chip area of the PLA efficiently