Title :
Test compression saves bits, cycles, and money
Abstract :
Test data compression became an active research topic in the late 1990s, and has now become a standard offering within commercial DFT solutions. This issue of IEEE Design & Test features a special issue on the current state of test compression. This issue of D&T also concludes the theme of design and test of RFIC chips (featured in the Jan./Feb. 08 issue), with two additional articles. In addition, this issue features two general-interest articles and an interview with DRAM inventor Bob Dennard.
Keywords :
Circuit testing; Clocks; Design for testability; Manufacturing processes; Moore´s Law; Random access memory; Semiconductor device testing; System testing; Test data compression; Variable speed drives; Bob Dennard; DFT; RFIC chips; test compression; test vectors;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2008.52
