Title :
Area-time efficient modulo 2n-1 adder design
Author :
Efstathiou, C. ; Nikolos, D. ; Kalamatianos, J.
Author_Institution :
Dept. of Telematics, Hellenic Telecommun. Org. SA, Athens, Greece
fDate :
7/1/1994 12:00:00 AM
Abstract :
In this paper the design of modulo 2n-1 adders is discussed. Two new design procedures are given, based on the one-level and the two-level carry look-ahead addition algorithms. The adders designed according to the procedures proposed in this paper are significantly more efficient, with respect to speed and the cost function area-time product, than the corresponding adders already known from open literature
Keywords :
VLSI; adders; carry logic; integrated logic circuits; logic design; cost function area-time product; design procedures; modulo 2n-1 adders; one-level carry look-ahead addition; residue number system; two-level carry look-ahead addition; Adders; Algorithm design and analysis; Circuits; Design methodology; Logic design; Multiplexing; Routing; Signal processing algorithms; Tin; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
