• DocumentCode
    112387
  • Title

    F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint

  • Author

    Jai-Ming Lin ; Ji-Heng Wu

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • Volume
    33
  • Issue
    11
  • fYear
    2014
  • fDate
    Nov. 2014
  • Firstpage
    1681
  • Lastpage
    1692
  • Abstract
    This paper presents a two-stage approach to handle fixed-outline floorplanning for mixed size modules, named F-FM. F-FM combines the advantages of the analytical approach and the slicing tree representation. Thus, it is not only suitable for handling fixed-outline floorplanning but also can be extended to handle other important issues in floorplanning such as routability or thermal effect in addition to wirelength. Recently, low power has become big challenges in very large-scale integration designs, which makes voltage-island driven floorplanning more important than ever. Although the problem has been discussed by previous works, no paper considers signal wirelength, powerplanning, and voltage drop at the same time under the fixed-outline constraint. Thus, this paper extends F-FM to handle this problem and consider these issues by properly dividing modules in a voltage domain into several islands. The experimental results show our approach obtains the best results in these problems.
  • Keywords
    VLSI; integrated circuit layout; mixed analogue-digital integrated circuits; F-FM; analytical approach; fixed-outline floorplanning methodology; mixed size modules; mixed-size modules; power planning; signal wirelength; slicing tree representation; thermal effect routability; two-stage approach; very large-scale integration designs; voltage domain; voltage drop; voltage-island constraint; voltage-island driven floorplanning; Complexity theory; Equations; Merging; Partitioning algorithms; Shape; System-on-chip; Timing; Fixed-outline; floorplanning; multiple supply voltage (MSV); voltage island;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2014.2351571
  • Filename
    6926920