Title :
Hierarchical Test Compression for SoC Designs
Author :
Kim, Kee Sup ; Zhang, Ming
Author_Institution :
Intel, Santa Clara
Abstract :
Capitalizing on the larger capacity of today´s ICs, designers are using yesterday´s chips as modules in today´s chips. DFT methodologies, which usually work on a large, flat design, must begin to take this reuse into account. This article shows how to use the X-compact compression technique in a hierarchical environment.
Keywords :
design for testability; system-on-chip; DFT methodologies; SoC designs; X-compact compression technique; hierarchical test compression; Analytical models; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Flip-flops; Logic design; Logic testing; SoC; hierarchical; test compression;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2008.39
