High-speed multi-input comparator

A comparison cell is presented that is able to compare n-data at a time and is based on dynamic logic methodology. The results of the n-data are sent to an m-bit NAND gate for the m×n comparison, where m corresponds to the word length of each datum. Compared to conventional comparators the proposed comparator requires fewer transistors and the circuit delay time is also shortened. To verify this comparator architecture, a 4-data×6-bit comparator is prototyped with only 66 transistors. The circuit delay time is only about 5 ns using the UMC 0.5 μm process. The fabricated chips have been successfully tested. Due to its regular structure, the comparison cell can be easily expanded to meet any required specification.