Title :
Layout Optimization of ESD Protection Diodes for High-Frequency I/Os
Author :
Bhatia, Karan ; Jack, Nathan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
Layout options for CMOS ESD diodes´ p-n junction geometry and metal routing are investigated in this paper. Experiments are performed using 90- and 180-nm technologies. Using the figures of merit ICP/C and R ON * C, it is shown that twin-well stripe diodes with nonminimum diffusion width and high-level broadside routing are optimum for gigahertz-frequency I/Os. In addition, the suitability of ESD diodes formed with the isolated P-well/deep N-well diffusions available in triple-well technologies is evaluated for high-speed I/O applications.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit metallisation; p-i-n diodes; semiconductor device metallisation; ESD protection diodes; layout optimization; metal routing; p-n junction; size 180 nm; size 90 nm; twin-well stripe diodes; CMOS integrated circuits; diodes; electrostatic discharges; metallization;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2009.2025956
