An analysis of virtual circuits with parallel links

Computer networks supporting virtual circuits deliver packets at the destination in the same sequence as they are received at the source. But packets may arrive at the destination out of sequence if the source is connected to the destination by multiple links. Consequently, in addition to queueing delay and service time (transmission delay) the packets suffer a resequencing delay. The sum of the queueing delay, service time, and resequencing delay is called the total delay. Assuming a Poisson stream of packets, a two-stage hyperexponential service time distribution and m equal capacity links connecting the source to the destination, the distribution and expected value of resequencing delay are derived here. With numerical examples it is shown that the mean total delay decreases very rapidly with the number of links m . The mean queueing delay increases rapidly with the mean service time, and the mean resequencing delay increases slowly with the mean service time