DocumentCode :
1126572
Title :
Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique
Author :
Yang, Bo ; Karri, Ramesh
Author_Institution :
Polytech. Univ. Brooklyn, Brooklyn
Volume :
26
Issue :
10
fYear :
2007
Firstpage :
1763
Lastpage :
1769
Abstract :
We present an architecture level low-power design technique called divide and concatenate for universal hash functions based on the following observations. (1) The power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant. (2) Two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach, we divide a w-bit data path (with collision probability2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w ). A popular low-power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.
Keywords :
circuit optimisation; clocks; low-power electronics; multiplying circuits; probability; bit array multiplier; clock rate; collision probability property; divide-and-concatenate technique; dynamic power consumption; low-power design; power optimization; universal hash function data path; Application software; Clocks; Data security; Databases; Energy consumption; Frequency; Hardware; Iterative algorithms; Search engines; Web search; Divide and concatenate; power optimization; universal hash function;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2007.896308
Filename :
4305260
Link To Document :
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