Earle latch design for high performance pipeline

A modified Earle latch, that requires only one copy of the input data instead of the two copies required in the original Earle scheme is presented. In SPICE simulations, the modified Earle latch has the smallest area and lowest power dissipation compared to other static latches. Chip implementation shows that the speed of an adder using the proposed latch outputs can be improved from 33 MHz to 60 MHz compared to the speeds obtainable using the original Earle latch.