Title :
SEU in SOI SRAMs-a static model
Author :
Musseau, O. ; Leray, J.L. ; Ferlet-Cavrois, V. ; Coïc, Y.M. ; Giffard, B.
Author_Institution :
CEA, Centre d´´Etudes de Bruyeres-le-Chatel, France
fDate :
6/1/1994 12:00:00 AM
Abstract :
The sensitivity to heavy ions of CMOS/SOI devices is mostly determined by the parasitic bipolar transistor that amplifies the deposited charge. A simple static model is proposed, which gives a relation between the LET threshold and the bipolar amplification factor β*. An analytical expression for β* versus transistor dimensions and ion LET is established, based on electrical measurements and numerical simulations on elementary transistors. Predictions from this model are in good agreement with experimental data obtained on SRAMs
Keywords :
CMOS integrated circuits; SRAM chips; amplification; equivalent circuits; ion beam effects; semiconductor device models; semiconductor-insulator boundaries; silicon; CMOS/SOI devices; LET threshold; SEU; SOI SRAMs; Si; bipolar amplification factor; heavy ion; ion LET; linear energy transfer; parasitic bipolar transistor; single event upset; static model; transistor dimensions; Analytical models; Bipolar transistors; CMOS technology; Electric variables measurement; MOS devices; MOSFETs; Numerical simulation; Semiconductor device modeling; Silicon; Voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
