Title :
Design and characterization of a standard cell set for delay insensitive VLSI design
Author :
De Gloria, Alessandro ; Faraboschi, Paolo ; Olivieri, Mauro
Author_Institution :
Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
fDate :
6/1/1994 12:00:00 AM
Abstract :
A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investigate the correspondence between theoretical formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We illustrate the new features involved in the electrical design and characterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cells have been fabricated
Keywords :
VLSI; cellular arrays; logic arrays; logic design; logic testing; sequential circuits; asynchronous circuits; circuit schematic; delay insensitive VLSI design; electric circuit operation; interconnection delays; standard cell set; Capacitance; Circuit synthesis; Costs; Delay systems; Electric resistance; Immune system; Integrated circuit interconnections; Very large scale integration; Voltage; Wire;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
