DocumentCode
1129086
Title
Instruction scheduler generation for retargetable compilation
Author
Wahlen, Oliver ; Hohenauer, Manuel ; Leupers, Rainer ; Meyr, Heinrich
Author_Institution
Aachen Univ. of Technol., Germany
Volume
20
Issue
1
fYear
2003
Firstpage
34
Lastpage
41
Abstract
The availability of C compilers is crucial to the efficient design of embedded systems. Using virtual resources to automatically generate parts of a compiler´s instruction scheduler from a formal processor description significantly reduces the overall scheduler generation time.
Keywords
embedded systems; processor scheduling; program compilers; C compilers; automatic instruction scheduler generation; embedded systems; formal processor description; retargetable compilation; Availability; Computational modeling; Computer architecture; Context modeling; Delay; Embedded system; Hardware; Processor scheduling; Software tools; VLIW;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2003.1173051
Filename
1173051
Link To Document