• DocumentCode
    1129092
  • Title

    Testing and characterization of SDRAMs

  • Author

    Vollrath, Jöerg E.

  • Author_Institution
    Infineon Technol. AG, Munchen, Germany
  • Volume
    20
  • Issue
    1
  • fYear
    2003
  • Firstpage
    42
  • Lastpage
    50
  • Abstract
    To improve yield and product quality, SDRAM manufacturers perform a variety of tests. A test sequence that incorporates retention tests, signal margin tests, and speed tests can help manufacturers find and repair weak memory cells.
  • Keywords
    DRAM chips; integrated circuit testing; SDRAM testing; retention tests; signal margin tests; speed tests; test sequence; weak memory cell repair; Circuit testing; Clocks; Content addressable storage; Decoding; Delay; Manufacturing; SDRAM; Semiconductor device measurement; Signal processing; Timing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1173052
  • Filename
    1173052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1129092