A CMOS high-speed wide-range programmable counter

Author

Lee, Sang-Hoon ; Park, Hong June

Author_Institution

Electr. & Comput. Eng. Div., Pohang Univ. of Sci. & Technol., Kyungbuk, South Korea

Volume

49

Issue

9

fYear

2002

fDate

9/1/2002 12:00:00 AM

Firstpage

638

Lastpage

642

Abstract

A CMOS high speed wide-range programmable divide-by-N counter was designed and the performance was verified by SPICE simulations and the measurements on the fabricated chip. A new reloading scheme and the use of simplified circuits for three least significant bit flip-flops enabled the high-speed operation of the proposed counter, independently of the number of counter stages. The proposed and Chang´s counters were fabricated on the same chip using a 0.6-μm triple-metal CMOS technology. The proposed and Chang´s counters with six stages were measured to work up to the clock frequencies of 1.34 GHz and 930 MHz, respectively.

Keywords

CMOS logic circuits; counting circuits; flip-flops; frequency dividers; frequency synthesizers; high-speed integrated circuits; programmable circuits; 0.6 micron; 1.34 GHz; 930 MHz; CMOS high speed counter; SPICE simulations; digital circuits; divide-by-N counter; high-speed operation; least significant bit flip-flops; reloading scheme; triple-metal CMOS technology; wide-range programmable counter; CMOS technology; Clocks; Counting circuits; Detectors; Flip-flops; Frequency conversion; Frequency synthesizers; SPICE; Semiconductor device measurement; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2002.805627

Filename

1174087