• DocumentCode
    1130188
  • Title

    Damage-Less Sputter Depositions by Plasma Charge Trap for Metal Gate Technologies

  • Author

    Takeuchi, Hideki ; She, Min ; Watanabe, Kozo ; King, Tsu-Jae

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
  • Volume
    18
  • Issue
    3
  • fYear
    2005
  • Firstpage
    350
  • Lastpage
    354
  • Abstract
    Damage-free sputter deposition process has been developed for metal gate complementary metal-oxide-semiconductor technology. A plasma charge trap (PCT) was introduced in order to eliminate high-energy particle bombardment during sputter deposition processes. Molybdenum (Mo)-gated PMOSFETs were fabricated using a conventional gate-first process. It is shown that the PCT technology yields excellent characteristics in current drivability, as well as in gate oxide integrity (GOI) such as gate leakage current and charge-to-breakdown (Q_BD) . The metal gate was also applied to a nonvolatile memory (NVM), which would require most stringent damage control, and good retention characteristics were demonstrated.
  • Keywords
    MIS devices; leakage currents; molybdenum; random-access storage; semiconductor device manufacture; sputter deposition; CMOS; Mo; PMOSFET; charge to breakdown; complementary metal oxide semiconductor; damage less sputter depositions; gate first process; gate leakage current; gate oxide integrity; metal gate technology; nonvolatile memory; plasma charge trap; Boron; CMOS technology; Capacitance; Dielectrics; Electrodes; Nitrogen; Nonvolatile memory; Plasmas; Silicon; Sputtering; Metal gate; molybdenum; sputtering;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2005.852094
  • Filename
    1492449