Title :
Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology
Author :
Rodoni, L.C. ; Ellinger, F. ; Jäckel, H.
Author_Institution :
Electron. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
Abstract :
Very low gate delays of 7.7 ps at 1 V supply and 4.7 ps at 2 V supply have been achieved for CMOS inverters fabricated on a 90 nm silicon on insulator technology. The results are measured with an optimised CMOS ring oscillator. These are believed to be the lowest gate delays reported to date for CMOS inverters at room temperature.
Keywords :
CMOS integrated circuits; delay circuits; elemental semiconductors; high-speed integrated circuits; integrated circuit layout; invertors; oscillators; silicon-on-insulator; 1 V; 2 V; 293 to 298 K; 4.7 ps; 7.7 ps; 90 nm; SOI technology; Si; gate delay fabrication; optimised CMOS ring oscillator; room temperature; silicon on insulator technology; ultrafast CMOS inverter;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20046031
