Analysis of BiCMOS buffer for input voltages with finite rise time

Author

Zhang, Shayan ; Kalkur, T.S.

Author_Institution

Adv. Technol. Dev. Lab., Motorola Inc., Austin, TX, USA

Volume

29

Issue

7

fYear

1994

fDate

7/1/1994 12:00:00 AM

Firstpage

797

Lastpage

807

Abstract

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design

Keywords

BiCMOS integrated circuits; SPICE; VLSI; buffer circuits; circuit analysis computing; delays; equivalent circuits; integrated logic circuits; logic gates; transient response; BiCMOS buffer; SPICE simulations; ULSI circuit design; circuit delay constants; digital logic gate; fan-in; fan-out; finite fall time; finite rise time; gate delay model; input signal slew rate; input slope; input voltages; timing analyzers; timing simulators; Analytical models; BiCMOS integrated circuits; Circuit simulation; Circuit synthesis; Delay effects; Logic gates; SPICE; Timing; Ultra large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.303717

Filename

303717