Title :
Simplifying sequential circuit test generation
Author :
Sheu, Meng-Lieh ; Lee, Chung Len
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Controllability; Degradation; Design for testability; Flip-flops; Hardware; Sequential analysis; Sequential circuits;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.1994.303845
