Implementation of an Experimental Fault-Tolerant Memory System

Author

Carter, William C. ; McCarthy, Charles E.

Author_Institution

IBM Thomas J. Watson Research Center

Issue

6

fYear

1976

fDate

6/1/1976 12:00:00 AM

Firstpage

557

Lastpage

568

Abstract

The experimental fault-tolerant memory system described in this paper has been designed to enable the modular addition of spares, to validate the theoretical fault-secure and self-testing properties of the translator/corrector, to provide a basis for experiments using the new testing and correction processes for recovery, and to determine the practicality of such systems. The hardware design and implementation are described, together with methods of fault insertion. The hardware/ software interface, including a restricted single error correction/double error detection (SEC/DED) code, is specified. Procedures are carefully described which, 1) test for specified physical faults, 2) ensure that single error corrections are not miscorrections due to triple faults, and 3) enable recovery from double errors.

Keywords

Decoding, diagnostics, encoding, error correction, error detection, fault-tolerant computing, memory with standby sparing, recovery, self-checking translators, switching algorithms.; Built-in self-test; Circuit faults; Computer errors; Encoding; Error correction; Error correction codes; Fault detection; Fault tolerant systems; Hardware; Testing; Decoding, diagnostics, encoding, error correction, error detection, fault-tolerant computing, memory with standby sparing, recovery, self-checking translators, switching algorithms.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1976.1674655

Filename

1674655