Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations and measurements. For 65 nm LP-CMOS, a close correlation has been obtained over a large frequency range from 10 MHz up to 10 GHz. Furthermore, we introduce the maximum decap admittance as a new metric for decap performance qualification. Closed-form expressions have been derived to calculate maximum admittance. Finally, we determine the relationship between relevant figure-of-merit parameters for decap design optimization.