An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$ m CMOS

Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write noise margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 times 20 bit eSRAM unit is implemented in a regular 0.13 mum CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% noise margin enhancement for this scheme when a subthreshold cell is accessed.