Title :
The Error Latency of a Fault in a Sequential Digital Circuit
Author :
Shedletsky, John J. ; McCluskey, Edward J.
Author_Institution :
Digital Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University
fDate :
6/1/1976 12:00:00 AM
Abstract :
In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented.
Keywords :
Error latency, input probability, latency interval, Markov chain, random testing, sequential circuits.; Circuit faults; Circuit testing; Clocks; Delay; Digital circuits; Error analysis; Pulse circuits; Random processes; Sequential analysis; Sequential circuits; Error latency, input probability, latency interval, Markov chain, random testing, sequential circuits.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1976.1674668
