Fast Low Power eDRAM Hierarchical Differential Sense Amplifier

In this paper, a hierarchical differential sense amplifier for fast, low power DRAM arrays in logic-based eDRAM technology that operates with large parameter variations is described. Unique features of the hierarchical sense amplifier include its short local bit lines and a local half sense amplifier p device latch that is connected by a switch to a global half sense amplifier device latch. When the local and global half latches are connected by the switch, they form a conventional cross-coupled latch. As a result of the short bit lines, the magnitude of the differential signal is large enough to overcome device variations in the various pairs of like-devices of the sense amplifier. The differential sense amplifier is quite insensitive to absolute parameter variation and mainly sensitive to mismatches between paired devices. The hierarchical differential sense amplifier has very low static power due to the use of a sense voltage of approximately Vdd/2 which causes low leakage in the local and global sense amplifiers as well as in the storage cell. Low active power also results from this Vdd/2 sensing. In addition, simulation results show low latency, fast restore, and fast cycle time with clocking and timing that are relatively simple.