On-chip ramp generators for mixed-signal BIST and ADC self-test

Author

Provost, Benoit ; Sánchez-Sinencio, Edgar

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

38

Issue

2

fYear

2003

fDate

2/1/2003 12:00:00 AM

Firstpage

263

Lastpage

273

Abstract

A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of ±175μV. Experimental and theoretical results are in good agreement.

Keywords

adaptive systems; analogue integrated circuits; analogue-digital conversion; built-in self test; calibration; integrated circuit testing; mixed analogue-digital integrated circuits; programmable circuits; ramp generators; ADC self-test; analog discrete-time adaptive scheme; built-in self-test; histogram-based tests; mixed-signal BIST; monotonicity; on-chip precise analog ramps; on-chip ramp generators; ramp generator calibration; slow analog ramps; time-domain analog testing; Analog circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Linearity; Performance evaluation; Signal generators; System testing; Time domain analysis;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.807415

Filename

1175507