DocumentCode :
1133317
Title :
A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme
Author :
Kim, Jung Pill ; Yang, Woodward ; Tan, Han-Yuan
Volume :
38
Issue :
2
fYear :
2003
fDate :
2/1/2003 12:00:00 AM
Firstpage :
329
Lastpage :
337
Abstract :
In order to achieve small self-refresh current (ICC6), the first 256-Mb SDRAM with an on-chip thermometer in the DRAM industry is implemented with a new self-refresh scheme. In addition, the biased reference line (BRL) sensing scheme improving refresh characteristics is proposed to increase refresh period and reduce ICC6. The on-chip thermometer is characterized by a small area of 0.43 mm2, low power consumption with less than 1-μA average current, and good accuracy of 5.85°C in the worst case. Good accuracy is achieved by incorporating many generic design techniques, including offset-free operational amplifiers and the chopping method, and small area is achieved by applying DRAM cell technology to integrating analog-digital converter. A 75% reduction in ICC6 at 60°C is achieved with on-chip thermometer and BRL sensing scheme improving 30% of refresh characteristic.
Keywords :
CMOS memory circuits; DRAM chips; analogue-digital conversion; low-power electronics; temperature sensors; thermometers; 1 muA; 256 Mbit; 60 degC; ADC; DRAM cell technology; ICC6 reduction; analog-digital converter; biased reference line sensing scheme; chopping method; design techniques; low power consumption; low-power SDRAM; offset-free opamp; on-chip thermometer; operational amplifiers; refresh characteristics; refresh period; self-refresh current; synchronous DRAM; Detectors; Handheld computers; Leakage current; Monitoring; Random access memory; SDRAM; Temperature; Testing; Voltage; Wood industry;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2002.807170
Filename :
1175514
Link To Document :
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