Analog timing recovery for a noise-predictive decision-feedback equalizer

Author

Keane, John P. ; Le, Michael Q. ; Hurst, Paul J.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA

Volume

38

Issue

2

fYear

2003

fDate

2/1/2003 12:00:00 AM

Firstpage

338

Lastpage

342

Abstract

A timing recovery architecture and its CMOS implementation are described for a noise-predictive decision-feedback equalizer (NPDFE). The 0.5-μm CMOS prototype includes timing recovery and the NPDFE and operates at 160 Mbit/s. The timing recovery blocks dissipate 27 mW from 3.3 V, occupy 0.2 mm², and achieve a root mean square jitter of 50 ps, which is 0.8% of a bit period.

Keywords

CMOS integrated circuits; decision feedback equalisers; digital magnetic recording; integrated circuit noise; mixed analogue-digital integrated circuits; synchronisation; 0.5 micron; 160 Mbit/s; 27 mW; 3.3 V; ASIC; CMOS implementation; analog timing recovery; communication applications; decision-feedback equalizer; digital communication systems; magnetic recording channel; mixed analog-digital IC; noise-predictive DFE; timing recovery architecture; Analog integrated circuits; Clocks; Decision feedback equalizers; Finite impulse response filter; Intersymbol interference; Magnetic noise; Prototypes; Semiconductor device noise; Signal to noise ratio; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.807171

Filename

1175515